1. Field of the Invention
The present invention relates to a semiconductor device having a memory function.
2. Description of Related Art
An equivalent circuit of a bit (hereinafter referred to as cell) of a dynamic random access memory (hereinafter referred to as a DRAM) of an LSI consists of a transistor T and a capacitor C.sub.s, as shown in FIG. 1. The capacitor C.sub.s is connected to the source electrode of the transistor T, while the drain electrode of the transistor T is connected to a data line and the gate electrode is connected to a word line. Information is stored as a "1" (high level) or a "0" (low level) according to whether or not the capacitor C.sub.s has a charge stored therein.
When the information is read, the word line is changed to a high level, and the transistor T is turned on. Then, the charge Q.sub.s stored in the capacitor C.sub.s flows through the transistor T to the data line, and the charge Q.sub.s of the memory cell and the charge stored in the data line capacitor C.sub.B are redistributed to change the electrical potential of the data line. This change in the electrical potential is amplified by a sense amplifier A for providing an output. At this time, the charge Q.sub.s stored in the capacitor C.sub.s vanishes. Therefore, the information must be restored by feeding back the amplified signal from the sense amplifier A to the data line in order to a again write in the memory cell.
FIGS. 2 and 3 show examples of sectional views of memory cells. In a trench type memory cell shown in FIG. 2, a capacitor part 2 of memory cell to be connected to a switching transistor part 1 is dug deep into the substrate 3, and a charge is stored between the substrate 3 and an electrode 4. In a stack type memory cell shown in FIG. 3, a transistor part 1' of memory cell is formed on a substrate 3', while a capacitor part is stacked above the transistor part 1'. The capacitor part 2' consists of two electrodes 4 and 4'.
In such DRAMs as explained above, as shown in FIG. 4, the cell size of 256M bit memory is about 0.8 .mu.m.sup.2 and that of 1 G bit memory is about 0.3 .mu.m.sup.2 if extrapolated from the cell sizes of 1M, 4M, 16M bit memories. If the cell size becomes very small as estimated above, the areas of the source and drain electrodes to be connected to the capacitor part or the metallizations is as small as 0.1 .mu.m.sup.2 by assuming that a MOS transistor used for a DRAM consists essentially of a source, a drain and a gate electrodes and that the cell area is simply divided into three. Thus, the size for forming metallizations becomes extremely small.
Further, as shown in FIG. 5, charges of about 3.times. 10.sup.5 electrons for storage is needed per cell by using a similar extrapolation. As shown in FIG. 6, the area of charge storage region for a capacitor in a 1 G bit DRAM is about 1-3 .mu.m.sup.2 by assuming that the thickness of a capacitor insulating film in a capacitor part is 5 nm of SiO.sub.2. Then, the area of a charge storage region is expected to be three to ten times that of a cell. This means that a very deep trench is needed for a trench type DRAM, while a very highly stacked capacitor is needed for a stack type DRAM. Therefore, it is very difficult to realize a DRAM of 256M or more.